The rePLay Framework

The rePLay Framework is a general-purpose microprocessor architecture for the billion-transistors timeframe that attains high performance by optimizing a program as it executes. As a program executes on the rePLay hardware, a special logic structure identifies regions of the program as candidates for highly aggressive optimization. Another structure optimizes these regions and then stores them locally on-chip in a trace cache.

Whenever one of these locally-cached, highly optimized regions is executed, performance is potentially higher than if the corresponding original code executed. These regions are called frames: they are dynamically-identified regions of the instruction stream that probabilistically have a single entry point and a single exit point. This atomic property of frames allows high-yielding optimizations to be performed on them, in the same manner that an optimizing compiler performs aggressive code optimization on extended basic blocks. The performance potential of these optimizations increases with longer atomic regions. By generating frames dynamically, using information about branch biases and correlations, we can create frames consisting of many instructions, exhibiting a very high probability of complete execution, i.e., there is no early exit from the frame. Experimentally, we’ve observed average frame sizes of 60-80 instructions on commercial code with completion rates of over 98%. Furthermore, these frames are constructed from a single flow of control. That is, all instructions within a frame are control independent of each other.

Presentations:

• “rePLay: The phenomenon behind and the limits of dynamic optimization in hardware,” S. S. Lumetta, Nov 2003, University of Texas at Austin
• “rePLay: A Hardware Framework for Dynamic Optimization,” S. J. Patel, April 2004, University of Minnesota, Digital Technology Center

Publications:

• F. Spadini, B. Fahs, S. J. Patel, S. S. Lumetta
  "Improving Quasi-Dynamic Schedules using Region Slip,"
  Proceedings of the 1st International Symposium on Code Generation and Optimization, March 2003.
• B. Slechta, D. Crowe, B. Fahs, M. Fertig, G. Muthler, J. Quek, F. Spadini, S. J. Patel, S. S. Lumetta
  "Dynamic Optimization of Micro-Operations,"
  Proceedings of the 9th International Symposium on High-Performance Computer Architecture, February 2003.
• G. Muthler, D. Crowe, S. J. Patel, and S. S. Lumetta
  "Instruction Fetch Deferral using Static Slack,"
  Proceedings of the 35th International Symposium on Microarchitecture, November 2002.
• B. Fahs, S. Bose, M. Crum, B. Slechta, F. Spadini, T. Tung, S. J. Patel, and S. S. Lumetta
  "Performance Characterization of a Hardware Framework for Dynamic Optimization,"
  Proceedings of the 34th International Symposium on Microarchitecture, December 2001.
• Sanjay J. Patel and Steven S. Lumetta
  "rePLay: A Hardware Framework for Dynamic Optimization,"
  IEEE Transactions on Computers, June 2001.
• Sanjay J. Patel, Tony Tung, Satarupa Bose, and Matthew M. Crum,
  Increasing the Size of Atomic Instruction Blocks using Control Flow Assertions,"
  Proceedings of the 33rd International Symposium on Microarchitecture, December 2000.
• Sanjay J. Patel and Steven S. Lumetta,
  "rePLay : a Hardware Framework for Dynamic Program Optimization,"
  University of Illinois Technical Report, CRHC-99-16, December 1999.

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