General Microarchitecture Publications

• Todd Ehrhart and Sanjay J. Patel,
  “Reducing the Scheduling Critical Cycle using Wakeup Prediction,”
  Proceedings of the 10^th Symposium on High-Performance Computer Architecture, February 2004.

• Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu,
  “Beating In-Order Stalls with “Flea-Flicker” Two-Pass Pipelining,”
  Proceedings of the 36^th Annual International Symposium on Microarchitecture, December 2003.

• Steven S. Lumetta and Sanjay J. Patel,
  “Characterization of Essential Dynamic Instructions,”
  Proceedings of SIGMETRICS 2003, June 2003.

• Frederick A. Koopmans and Sanjay J. Patel,
  "Decoupled Pipelines: Rationale, Analysis, and Evaluation,"
  Workshop on Complexity-Effective Design, in conjuction with the 29th Annual International Symposium on Computer Architecture.

• Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, and Jared Stark,
  "One Billion Transistors, One Uniprocessor, One Chip,"
  IEEE Computer, September 1997.