ABSTRACT
In this CMP era, an abundant amount of compute parallelism is now available to
workloads for achieving high performance. However, as multiple threads, multiple
applications and/or multiple virtual machines run simultaneously on the platform,
they will contend on critical shared resources (such as shared cache space, memory
bandwidth and even socket power) and suffer performance determinism challenges.
This introduces the quality of service (QoS) challenge that needs to be addressed
to provide sufficient performance isolation and performance differentiation. In
this talk, I will describe our Platform QoS research that comprises of two key
components: (a) resource monitoring techniques for OS/VMM visibility into transparent
shared resource in the platform and (b) resource enforcement techniques for OS/VMM
to provide guidance on resource allocation. We will also introduce a class of
service interface that allows the OS/VMM to assign applications to classes of
service in order to enable resource differentiation. Using cache space and memory
bandwidth as the primary example, I will show how monitoring and enforcement techniques
can be implemented with minimal overhead and how they can be taken advantage of
by operating systems and virtual machine monitors to provide better QoS and potentially
better throughput as well. I will also describe a path to transforming virtual
machines (VMs) to be transformed into virtual platform architectures (VPAs) that
allow specification in terms of core, cache, memory and power resources.
BIOGRAPHY
Ravi Iyer is a Principal Research Scientist with the Systems Technology Lab
in Intel’s Corporate Technology Group. His current research focus is on
large-scale CMP architectures and technologies. Before joining STL, he held
positions in the Communications Technology Lab (working on IO acceleration research)
and in the Enterprise Products Group (working on server architecture and performance).
He received his Ph.D. in Computer Science from Texas A&M University. He
has filed 20+ patents and published 80+ papers in the areas of computer architecture,
server design, cache/memory hierarchies, QoS, reconfigurable architectures,
network protocols/acceleration, workload characterization and performance evaluation.
He has held program committee member positions in various conferences (HPCA,
PACT, ISPASS, IISWC, etc) and co-chaired workshops (CAECW). He is also an Associate
Editor for IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS)
and ACM Transactions on Architecture and Code Optimization (ACM TACO).