ABSTRACT
With the recent announcement of 45nm products we have confirmation that Moore's Law is still in force. Thus, we are about to see yet another large increase in the number of transistors that fit on a single chip. While this is a great opportunity, we have been observing increasing challenges in finding the most effective uses for these transistors. Design team size, mask costs and fabrication costs are all increasing, thus there is increasing desire to make the right decisions about which research ideas to bring forward to design. Unfortunately, our existing evaluation methodologies are proving increasingly ineffective at providing compelling evidence that a new idea warrants inclusion in future designs. In this talk, I will elaborate on these challenges and discuss some approaches to improve on our ability to prove the merit of architectural ideas. In particular, I will discuss an approach to using field-programmable gate arrays (FPGAs) as the basis for the modeling of future systems. Included in the discussion will be a practical approach to modularizing the model, separation of the functional and timing aspects of the simulation, and additional infrastructure important for performance modeling.

BIOGRAPHY
Dr. Joel S. Emer is an Intel Fellow working in the Digital Enterprise Group, where he is director of micro-architecture research. Before joining Intel he spent 22 years as a Digital/Compaq employee, where he worked on processor architecture, performance analysis and performance modeling methodologies for a number of VAX and Alpha CPUs. He is widely recognized for his architecture contributions, including pioneering efforts in simultaneous multithreading, and for his seminal work on the now pervasive quantitative approach to processor evaluation. He also has researched heterogeneous distributed systems and networked file systems at DEC and during a three year sabbatical at MIT. His current research interests include processor reliability, multithreaded processor organizations, techniques for increased
instruction level parallelism, pipeline organization, instruction and data cache organizations, branch prediction schemes, and performance modeling. Dr. Emer holds a Ph.D. in Electrical Engineering from the University of Illinois, and M.S.E.E. and B.S.E.E. degrees from Purdue University. He is also a Fellow of both the ACM and the IEEE.