In this talk, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS/Nano hybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4.5X footprint reduction comparing to the traditional CMOS-based 2D FPGAs. With a customized design automation flow, we evaluate the performance and power of 3D nFPGA driven by the 20 largest MCNC benchmarks. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6X with a small power overhead comparing to the CMOS 2D FPGA architecture. (This work is going to appear at ICCAD’07, and an extended version of the work is going to appear at TCAS-I).

BIOGRAPHY

Dr. Deming Chen received his BS in computer science from University of Pittsburgh, Pennsylvania in 1995 and worked for several years before he joined the Ph.D. program of UCLA in 1999. During his Ph.D., he worked as a software engineer at Aplus Design Technologies, Inc (now part of Magma Design Automation, Inc.) for more than a year. He joined the ECE department of UIUC as a faculty member in 2005. He has been actively publishing in high-level and logic synthesis, low power design, and FPGA design and synthesis in various leading CAD conferences and journals. Some of his research ideas have already been incorporated in commercial software (e.g., Altera and Magma). His current research interests include CAD for FPGA, nano-systems design and nano-centric synthesis, microprocessor architecture design under process variation, and reconfigurable computing. He is a technical committee member for FPGA'06-08, ASPDAC'07-08, ISCAS'07-08, and ICCD'07. He is a session chair for ICCD, ASPDAC, and ICCAD. Together with Guy Lemieux, he organized a workshop "Grand Challenges in FPGA Research" held in conjunction with FPGA'07.