Abstract: In future large-scale multi-core microprocessors, hard errors and process
variations will create dynamic heterogeneity, whereby performance and power characteristics
differ among the cores in an unanticipated manner. Under this scenario, naïve
assignments of applications to cores degraded by various faults and variations
may result in large performance losses and power inefficiencies. We propose scheduling
algorithms based on Artificial Intelligence search techniques that account for
this future uncertainty in core characteristics. These thread assignment policies
effectively match the capabilities of each degraded core with the requirements
of the applications, achieving a power-performance efficiency on par with a baseline
eight core chip multiprocessor with no degradation. We also discuss our recent
work in efficiently marrying reconfigurable logic with chip multiprocessors.
Biography: Dave Albonesi is an Associate Professor in the School of Electrical
and Computer Engineering and a member of the Computer Systems Laboratory. Prior
to joining Cornell in 2004, he spent eight years as a faculty member at the
University of Rochester, and ten years in management and development in the
computer industry. His research group investigates adaptive, power-efficient,
and reliability-aware computer architectures, and multicore architectures exploiting
new technologies.