Ronald D. Barnes

Publications Beating in-order stalls with "flea-flicker" two-pass pipelining
Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro and Wen-mei W. Hwu
to appear in IEEE Transactions on Computers, Special Issue on Embedded Systems, Microarchitecture, and Compilation Techniques in Memory of Bob Rau, Vol. 55, No. 2, February 2006.

Multiple-Pass Pipelining: Enhancing in-order Microarchitectures to Out-Of-Order Performance(PDF version)
Ronald D. Barnes, JR.
PhD thesis, Department of Electrical and computer Engineering, University of Illinois, Urbana IL, 2005

Multipass "Flea-Flicker" Pipelining
Ronald D. Barnes, and Wen-mei W. Hwu
to appear in Proceedings of the 4th Workshop on Explicitly Parallel Instruction Computing Architectures, March 2005.

EPIC's Future: Exploring the Space Between In- and Out-of-Order
Ronald D. Barnes, John W. Sias, Erik M. Nystrom and Wen-mei W. Hwu
presented at The 4th Workshop on Explicitly Parallel Instruction Computing Architectures, Palo Alto, California, March 2004.

Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining(available online at IEEE and ACM)
Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro and Wen-mei W. Hwu
Proceedings of the 36th Annual International Symposium on Microarchitecture, pp. 387-398, December 2003.

Phase Profiling in Managed Code Environments
Ronald D. Barnes, Marie T. Conte, Erik M. Nystrom and Wen-mei W. Hwu
presented at The 1st Workshop on Managed Run Time Workloads, San Francisco, California, March 2003.

Compaction Algorithm for Precise Modular Context-Sensitive Pointer Analysis(PS version PDF version)
Hong-Seok Kim, Erik M. Nystrom, Ronald D. Barnes and Wen-mei W. Hwu
IMPACT Technical Report, IMPACT-03-03, University of Illinois, Urbana, IL 2003.

Extracting Hardware-Detected Program Phases for Post-Link Optimization
Ronald D. Barnes
Master's thesis, University of Illinois, Urbana, IL 2002.

Vacuum Packing: Extracting Hardware-Detected Program Phases for Post-Link Optiminzation(available online at IEEE and ACM)
Ronald D. Barnes, Erik M. Nystrom, Matthew C. Merten and Wen-mei W. Hwu
Proceedings of the 35th Annual International Symposium on Microarchitecture, pp. 233-244, December 2002.

Itanium performance insights(PDF slides PS handouts PDF handouts)
Wen-mei W. Hwu, John W. Sias, Matthew C. Merten, Erik M. Nystrom, Ronald D. Barnes, Christopher J. Shannon, Shane Ryoo and Jeff V. Olivier
Presentation at Microprocessor Forum, October 2001.

Code Reordering and Speculation Support for Dynamic Optimization Systems(PS version PDF version)
Erik M. Nystrom, Ronald D. Barnes, Matthew C. Merten and Wen-mei W. Hwu
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, pp. 163-174, September, 2001.

Itanium performance insights from the IMPACT Compiler(PDF slides PS handouts PDF handouts)
John W. Sias, Matthew C. Merten, Erik M. Nystrom, Ronald D. Barnes, Christopher J. Shannon, Joe D. Matarazzo, Shane Ryoo, Jeff V. Olivier and Wen-mei W. Hwu
Presentation at Hot Chips 13, August 2001.

An Architectural Framework for Run-Time Optimization (PS version PDF version)
Matthew C. Merten, Andrew R. Trick, Ronald D. Barnes, Erik M. Nystrom, Christopher N. George, John C. Gyllenhaal and Wen-mei W. Hwu
IEEE Transactions on Computers, Vol. 50, No. 6, pp. 567-589, June 2001.

A Hardware Mechanism for Dynamic Extraction and Relayout of Program Hot Spots(PS version PDF version)
Matthew C. Merten, Andrew R. Trick, Erik M. Nystrom, Ronald D. Barnes, and Wen-mei W. Hwu
Proceedings of the 27th International Symposium on Computer Architecture, pp. 59-70, June 2000.