ECE 411 / CA 718-Q: Computer Microarchitecture: Hardware
and Software
General Course Info
The final exam in now available. [ pdf
] [ ps ]
On-campus students: Video tape copies of the lectures will be placed
at the reserve desk of Grainger Library. The videos are available for 2
hour checkout periods for viewing at the library's in-house VCRs. Copies
of the tapes CANNOT be made.
Announcements
-
04/01/99 Presentation slides from Dan Lavery's (Intel) talk
on IA-64 are available in Acrobat form. [ pdf
]
-
02/19/99 Reading sets 4-7 have been sent to the library and
should be available later today.
-
02/10/99 A test message has been sent to all students currently
on the email list. If you haven't received the test message then you probably
haven't sent your contact information as requested in the course syllabus.
If you want to be on the email list and haven't received the test message,
please send that information ASAP.
Slides
-
Introduction Lectures [ pdf
] [ ps ]
-
Ifetch Lectures [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
Out-Of-Order Lectures
-
Issue [ pdf ] [ ps
] extra figures [ pdf ] [ ps
]
-
Recovery [ pdf ] [
ps
]
-
Other OOO Cores [ pdf
] [ ps ]
-
Compiler Technology
-
Basic Techniques [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
Machine Description Technology [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
Software Pipelining [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
EPIC Architecture and Compiler Technology
-
VLIW Architecture [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
Speculation [ pdf ] [
ps
] extra figures [ pdf ] [ ps
]
-
Data Speculation [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
Speculation Heuristics [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
Predication [ pdf ] [
ps
] extra figures [ pdf ] [ ps
]
-
Predication Optimization (4/5/99 Updated lecture) [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
Partial Predication [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
Predication and Speculation [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
Machine Description Optimization [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
Memory Systems
-
Advanced Cache Microarchitecture [ pdf
] [ ps ] extra figures [ pdf
] [ ps ]
-
Emerging DRAM Technologies [ pdf
] [ ps ]
-
Other Microarchitectures
Homework
Papers
-
Reading 1: Instruction Fetch and Branch Prediction
-
T-Y Yeh and Y. N. Patt. "Alternative implementation of two-level
adaptive branch prediction." In Proceedings of the 19th International
Symposium on Computer Architecture, pages 124-134, May 1992. [ unavailable
online ]
-
T-Y Yeh and Y. N. Patt. "A comprehensive instruction fetch
mechanism for a processor supporting speculative execution." In Proceedings
of the 25th Annual International Symposium on Microarchitecture, pages
129-139, Portland, OR, December 1992. [ unavailable online ]
-
S. Pan, K. So, and J. T. Rahmeh. "Improving the accuracy
of dynamic branch prediction using branch correlation." In Proceedings
of the 5th International Conference on Architectural Support for Programming
Languages and Operating Systems , pages 76-84, October 1992. [ unavailable
online ]
-
P. M. Mills T. M. Conte, K. N. Menezes, and B. A. Patel.
"Optimization of instruction fetch mechanisms for high issue rates." In
Proceedings
of the 24th Annual International Symposium on Computer Architecture,
pages 333-344, June 1995. [ ps
]
-
Reading 2: Instruction Issue
-
R. M. Tomasulo. "An efficient algorithm for exploiting multiple
arithmetic units." In IBM Journal of Research and Development, 11:25-33,
January 1967. [ unavailable online ]
-
Y. N. Patt, W. Hwu, and M. Shebanow. "Hps, a new microarchitecture:
Rationale and introduction." In Proceedings of the 18th Workshop on
Microprogramming, pages 103-108, 1985. [ unavailable online ]
-
Y. N. Patt, W. Hwu, and M. Shebanow. "Critical issues regarding
hps, a high performance micro architecture." In Proceedings of the 18th
Workshop on Microprogramming, pages 109-116, 1985. [ unavailable online
]
-
S. Weiss and J. E. Smith. "Instruction issue logic in pipelined
supercomputers." In IEEE Transactions on Computers, C-33:1013-1022,
November 1984. [ unavailable online ]
-
W. W. Hwu and Y. N. Patt. "HPSm, a high performance restricted
data flow architecture having minimal functionality." In Proceedings
of the 13th International Symposium on Computer Architecture, pages
297-306, June 1986. [ unavailable online ]
-
G. S. Sohi and S. Vajapeyam. "Instruction issue logic for
high-performance interruptable pipelined processors." In Proceedings
of the 14th Annual Symposium on Computer Architecture, pages 27-34,
June 1987. [ unavailable online ]
-
Reading 3: State Recovery
-
J. E. Smith and A. R. Pleszkun. "Implementation of precise
interrupts in pipelined processors." In Proceedings of the 12th Annual
International Symposium on Computer Architecture, pages 36-44, June
1985. [ unavailable online ]
-
W. W. Hwu and Y. N. Patt. "Checkpoint repair for high performance
out-of-order execution machines." In IEEE Transaction on Computers,
C-36:1496-1514, December 1987. [ unavailable online ]
-
Reading 4: Supplemental Wide Issue
-
E. Rotenberg, S. Bennett, J.E. Smith. "Trace Cache: A Low
Latency Approach to High Bandwidth Instruction Fetching." In Proceedings
of the 29th ACM/IEEE International Symposium on Microarchitecture,
December 1996, Paris, France, pp. 24-34.
-
S. Patel and Y. Patt. "Improving Trace Cache Effectiveness
with Branch Promotion and Trace Packing," In Proceedings of the 25th
International Symposium on Computer Architecture, July 1998, Barcelona,
Spain, pp. 262-271.
-
Reading 5: Acyclic Scheduling
-
M. Tokoro, E. Tamura, and T. Takizuka. "Optimization of Microprograms,"
In IEEE Transaction on Computers, Vol. C-30, No. 7, July 1981.
-
J. A. Fisher. "Trace scheduling: A technique for global microcode
compaction." In IEEE Transactions on Computers, C-30:478-490, July
1981.
-
W. W. Hwu, S. A. Mahlke, W. Y. Chen, P. P. Chang, N. J. Warter,
R. A. Bringmann, R. G. Ouellette, R. E. Hank, T. Kiyohara, G. E. Haab,
J. G. Holm, and D. M. Lavery. "The Superblock: An Effective Technique for
VLIW and Superscalar Compilation" In The Journal of Supercomputing,
Kluwer Academic Publishers, 7, 1993, pp. 229-248.
-
Reading 6: Modulo Scheduling
-
B. R. Rau, M. S. Schlansker, and P. P. Tirumalai. "Code generation
schema for modulo scheduled loops." In Proceedings of the 25th Annual
International Symposium on Microarchitecture, pages 158-169, December
1992.
-
B. R. Rau. "Iterative modulo scheduling: An algorithm for
software pipelining loops." In Proceedings of the 27th International
Symposium on Microarchitecture, pages 63-74, December 1994.
-
D. M. Lavery and W. W. Hwu. "Modulo Scheduling of Loops in
Control-Intensive Non-Numeric Programs," In Proceedings of the 29th
ACM/IEEE International Symposium on Microarchitecture, pp. 126-137.
-
Reading 7: Machine Description
-
J. C. Gyllenhaal, W. W. Hwu, and B. R. Rau, "Optimization
of Machine Descriptions for Efficient Use," In International Journal
of Parallel Programming, Special issue on the most significant papers from
the ACM/IEEE International Symposium on Microarchitecture, Vol. 26,
No. 4, August 1998.
-
V. Bala and N. Rubin. "Efficient Instruction Scheduling Using
Finite State Automata," In International Journal of Parallel Programming,
Special issue on the most significant papers from the ACM/IEEE International
Symposium on Microarchitecture, Vol. 25, No. 2, April 1997.
-
Reading 8: Compiler Technology and Compile-time Speculation
and Predication 1
-
W. W. Hwu, et al, "Compiler Technology for Future Microprocessors,"
In IEEE Proceedings, Vol. 83, No. 12, December 1995.
-
P.P. Chang, N.J. Warter, S.A. Mahlke, W.Y. Chen, and W.W.
Hwu. "Three architectural models for compiler-controlled speculative execution."
IEEE Transactions on Computers, 44(4):481-494, April 1995.
-
S. A. Mahlke, W. Y. Chen, R. Bringmann, R. Hank, W. W. Hwu,
M. Schlansker and B. Rau, "Sentinel Scheduling: A Model for Compiler-Controlled
Speculative Execution," In ACM Transactions on Computer Systems,
vol. 11, No. 4, November, 1993, pp. 376-408.
-
D.M. Gallagher, W.Y. Chen, S.A. Mahlke, J.C. Gyllenhaal,
and W.W. Hwu. Dynamic memory disambiguation using the memory conflict buffer.
In Proceedings of 6th International Conference on Architectual Support
for Programming Languages and Operating Systems, pages 183-193, October
1994.
-
J.C. Park and M.S. Schlansker. "On predicated execution,"
Technical Report HPL-91-58, Hewlett Packard Laboratories, Palo Alto, CA,
May 1991.
-
S.A. Mahlke, D.C. Lin, W.Y. Chen, R.E. Hank, and R.A. Bringmann.
"Effective compiler support for predicated execution using the hyperblock."
In Proceedings of the 25th International Symposium on Microarchitecture,
pages 45-54, December 1992.
-
Reading 9: Compile-time Speculation and Predication 2 and
Advanced ILP Optimizations
-
S. A. Mahlke, R. E. Hank, J. E. MCormick, D. I. August, W.
W. Hwu, "A Comparison of Full and Partial Predicated Execution Support
for ILP Processors," In Proceedings of the 22nd Annual International
Symposium on Computer Architecture , Santa Margherita Ligure, Italy,
June 1995, pp. 138-150.
-
R.P. Colwell, R.P. Nix, J.J. O'Donnell, D.B. Papworth, and
P.K. Rodman. "A VLIW architecture for a trace scheduling compiler." In
Proceedings
of the 2nd International Conference on Architectural Support for Programming
Languages and Operating Systems, pages 180-192, April 1987.
-
B.R. Rau, D.W.L. Yen, W.Yen, and R.A. Towle, The "Cydra 5
departmental supercomputer," IEEE Computer, 22(1):12-35, January 1989.
-
J.C. Dehnert, P.Y. Hsu, and J.P. Bratt, "Overlapped loop
support in the Cydra-5," In Proceedings of the Third International Conference
on Architectural Support for Programming Languages and Operating Systems,
pages 26-38, April 1989.
-
D.I. August, D. Connors, S. A. Mahlke, J. Sias, K. Crozier,
B. Cheng, P. Eaton, Q. Olaniran, W. W. Hwu, "Integrated Predicated and
Speculative Execution in the IMPACT EPIC Architecture," In Proceedings
of the 25th Annual International Symposium on Computer Architecture (ISCA),
June 27 - July 1, 1998, Barcelona, Spain, pp. 227-237.
-
M.Schlansker and V.Kathail, "Critical path reduction for
scalar programs," In Proceedings of the 28th International Symposium
on Microarchitecture, pages 57-69, December 1995.
-
D.I. August, J.W. Sias, J.M. Puiatti, K.M. Crozier, W.W.
Hwu, "The Program Decision Logic Approach to Utilizing Predicated Execution,"
in Proceedings of the 26th International Symposium on Computer Architecture,
Atlanta, GA, May 1999.
WWW Sites of Interest
All slides and figures © 1999 by Wen-mei Hwu. All rights
reserved.
ECE 411 / CA 718-Q web site created and maintained by Matthew
Merten ,
merten@crhc.uiuc.edu