This thesis presents a method for analyzing a register transfer level
(RTL) sequential circuit description to insert frozen clock
design-for-testability features into the circuit.  The frozen clock
testing strategy selectively freezes groups of registers so that the
sequential feedback paths in the circuit are cut during test
application, and various pipeline configurations are formed.  The
frozen clock test strategy applies tests at speed, has no performance
penalty, and has a low area overhead.

A new software tool, \fI fc_analyzer\fR, was developed to analyze the
RTL circuit description and determine which groups of registers should
be frozen together to break all global feedback cycles.  The \fI
fc_analyzer \fR tool parses the RTL description and extracts an RTL
structural graph (s-graph).  Next, \fI fc_analyzer \fR determines the
sequential feedback cycles in the s-graph.  Finally, for each global
cycle in the s-graph, a register is selected to break the feedback
cycle, and the resulting register groups for the frozen clock test
architecture are generated as output.  Experiments conducted on seven
benchmark circuits demonstrate that \fI fc_analyzer \fR is effective
in deriving the clock control logic for the frozen clock test
architecture.  Execution times are short, and the method is applicable
to large circuits.