TITLE: Test Time and Test Data Volume Reduction Techniques for VLSI
Circuits

AUTHOR: Amit Raj Pandey

ABSTRACT: Testing cost is becoming an important factor in the overall integrated
circuit (IC) manufacturing cost due to the exponential rise in
transistor count per chip as predicted by Moore's law.  This increases
the complexity of test, and the testing costs incurred by test pattern
generation and test application process. In this thesis, we address
the issue of decreasing test cost by lowering the test data bits and
the number of clock cycles required to test a chip.  We provide a
detailed analysis of test data and test time reduction in Illinois
Scan Architecture (ILS) based designs.  We propose a new incremental
algorithm for generating tests for ILS based designs.  This algorithm
is very efficient in generating tests for a number of ILS designs in
order to find the optimum configuration.  We also propose a
reconfigurable technique to reduce test time and test data volume. The
reconfigurable technique is introduced along with a detailed test
generation and test application procedure. We also discuss the
implementation issues for test application time reduction using a
counter-based built-in-self-test (BIST) system.