TITLE: Techniques for Reducing Diagnostic Simulation Time for Partial
Scan Circuits

AUTHOR: Scott Brady Drummonds

ABSTRACT: This thesis presents techniques that can be used to decrease
the execution time of diagnostic simulators on partial-scan circuits
using patterns generated with a sequential automatic test generation
engine.  The techniques are shown not to have a significant impact on
the resolution or accuracy of the diagnosis.  The proposed algorithms
reduce the simulated fault list through use of new input cone and the
concept of a simulation window.  The improved input code uses scan
information from the circuit and patterns to limit the input cone
traversal performed by a traditional input cone.  The simulation
window is used to block the simulation of patterns that are not
necessary in reproducing the observed failures.  These techniques were
implemented in a production diagnostic simulator and were tested with
simulation data on microprocessor blocks.  The results show that
computational effort can be reduced by an order of magnitude when
faulting only locations in the new input cone and block fault
simulation of out-of-window cycles.