TITLE: Automatic Bias Generation for Biased Random Instruction Generation

AUTHOR: Mrinal Bose

ABSTRACT: Biased random instruction generators are commonly used in
architectural verification of microprocessors, with biases specified
manually by designers. As the complexity of processors grows, so does
the complexity of specifying biases. Automatic bias generation speeds
up the verification flow and may lead to better coverage of potential
design errors. In this thesis, we present two algorithms for automatic
bias generation.

The first approach uses a genetic algorithm to optimize for the utilization
of specific buffers and the occurrence of specific events In the PowerPC
architecture. The second approach consists of a deterministic algorithm
to automatically generate biases that cover all pipeline states, where
each pipeline state represents the positions and types of instructions
in the pipeline. The algorithm has been tested on the PowerPC and
the ARM7 architectures. Experimental results show that automatically
generated biases outperform randomly generated test programs and biases
generated using a greedy hill-climbing algorithm. Of the two methods,
the genetic algorithm gives the best results but requires more execution
time.