Three Architectural Models for Compiler-Controlled Speculative Execution (PostScript version, PDF version)
P. P. Chang, N.J. Warter, S. A. Mahlke, W. Y. Chen, and W. W. Hwu
IEEE Transactions on Computers, Vol. 44, No. 4, April 1995, pp. 481-494
To effectively exploit instruction level parallelism,
the compiler must move instructions across branches.
Speculative execution refers to moving an instruction above
a conditional branch that the instruction is control
dependent upon. It is speculative execution since the
instruction is executed before it is known whether or not its
result is needed. There are potential hazards when
speculatively executing instructions. If these hazards
can be eliminated, the compiler can more aggressively schedule
the code. The hazards of speculative execution are outlined
in this paper. Three architectural models: restricted,
general and boosting, which have increasing amounts of support
for removing these hazards are discussed. The performance
gained by each level of additional architecture support is
analyzed using the IMPACT C compiler which performs superblock
scheduling for superscalar and superpipelined processors.
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