Data Access Microarchitectures for Superscalar Processor with Compiler-Assisted Data Prefetching (PostScript version, PDF version)
William Y. Chen, Scott A. Mahlke, Pohua P. Chang, and Wen-mei W. Hwu
Proceedings of the 24th Annual ACM/IEEE Int'l Symposium on Microarchitecture, Albuquerque, New Mexico, Nov. 1991, pp. 69-73
The performance of superscalar processors is more
sensitive to the memory system delay than their single-
issue predecessors. This paper examines alternative
data access microarchitectures that effectively support
compiler-assisted data prefetching in superscalar
processors. In particular, a prefetch buffer is shown
to be more effective than increasing the cache dimension
in solving the cache pollution problem. All in all, we
show that a small data cache with compiler-assisted data
prefetching can achieve a performance level close to that
of an ideal cache.
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