IGATE Research on Memory and Iterative Logic Array Testing

Key Contributors

• Janak Patel
• Elizabeth Rudnick
• Wu-Tung Cheng
• Pinaki Mazumder
• Dirk Niggemeyer

Research Papers

A listing of all published IGATE research papers on memory and iterative logic array testing is included below.

Diagnostic testing of embedded memories based on output tracing,
Dirk Niggemeyer, Michael Redeker, and Elizabeth M. Rudnick,
Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing, pp. 113-118, August 2000.

Diagnostic testing for embedded memory using BIST,
Timothy Bergfeld, Dirk Niggemeyer, and Elizabeth M. Rudnick,
Proceedings of the Design, Automation and Test in Europe (DATE) Conference, March 2000.

A comprehensive study of random testing for embedded RAMs using markov chains,
Pinaki Mazumder and Janak H. Patel,
Journal of Electronic Testing: Theory and Applications, vol. 3, no. 4,
pp. 235-250, Nov. 1992. Abstract

Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors,
A. Chatterjee, R. K. Roy, J. A. Abraham and Janak H. Patel,
Digital Signal Processing, vol. I, pp. 231-244, 1991.

A. Chatterjee, R. K. Roy, J. A. Abraham and Janak H. Patel,
Efficient testing techniques for bit and digit-serial arrays,
Proceedings of the 4th International Symposium on VLSI Design, pp 142-147, January 1991.

A reconfigurable parallel signature analyzer for concurrent error correction in DRAM,
Pinaki Mazumder, Janak H. Patel, and Jacob A. Abraham,
IEEE Journal of Solid-State Circuits, vol. 25, no. 3,
pp. 866-870, June 1990.
Abstract

An Efficient Built-In Self-Testing Algorithm for Random-Access Memory,
Pinaki Mazumder and Janak H. Patel,
IEEE Transactions on Industrial Electronics, vol. 36, no. 3,
pp. 394-407, May 1989.
Abstract

Diagnosis and repair of memory with coupling faults,
M.-F. Chang, W. Kent Fuchs, and Janak H. Patel,
IEEE Transactions on Computers, vol. 38, no. 4,
pp. 493-500, April 1989.

Parallel testing for pattern-sensitive faults in semiconductor random-access memories,
Pinaki Mazumder and Janak H. Patel,
IEEE Transactions on Computers, vol. 38, no. 3,
pp. 394-407, March 1989.
Abstract

An efficient design of embedded memories and their testability analysis using markov chains,
Pinaki Mazumder and Janak H. Patel,
IEEE International Conference on Wafer-Scale Integration,
Jan. 1989.
Abstract

Diagnosis and repair of memory with coupling faults,
M.-F. Chang, W. Kent Fuchs, and Janak H. Patel,
Proceedings of the International Conference on Computer-Aided Design,
pp. 524-527, November 1988.

Parallel testing of parametric faults in a DRAM,
Pinaki Mazumder and Janak H. Patel,
Proceedings of the Advanced Research in VLSI: 5th MIT Conference,
pp. 148-160, March 1988.
Abstract

Methodologies for testing embedded content addressable memories,
Pinaki Mazumder, Janak H. Patel, and W. Kent Fuchs,
IEEE Transactions on Computer-Aided Design of Circuits and Systems, vol. 7,
pp. 11-20, January 1988.
Abstract

Testing and fault-tolerant aspects of high-density VLSI memory,
Pinaki Mazumder,
Ph.D. dissertation, Department of Electrical Engineering,
Technical Report CSG-81/UILU-ENG-88-2206,
University of Illinois, 1988.
Abstract

A novel fault-tolerant design of testable dynamic random access memory,
Pinaki Mazumder and Janak H. Patel,
Proceedings of the International Conference on Computer Design,
pp. 306-309, October 1987.
Abstract

An efficient built-in self testing for random access memory,
Pinaki Mazumder and Janak H. Patel,
Proceedings of the International Test Conference,
pp. 1072-1077, September 1987.
Abstract

A minimum test set for multiple-fault detection in ripple-carry adders,
Wu-Tung Cheng and Janak H. Patel,
IEEE Transactions on Computers, vol. C-36,
pp. 891-895, July 1987.

Methodologies for testing embedded content addressable memories,
Pinaki Mazumder and Janak H. Patel,
Proceedings of the International Symposium on Fault-Tolerant Computing,
pp. 270-275, July 1987.
Abstract

Design and algorithms for parallel testing of random access and content addressable memories,
Pinaki Mazumder and Janak H. Patel,
Proceedings of the ACM/IEEE Design Automation Conference,
pp. 688-694, June 1987.
Abstract

Testing in two-dimensional iterative logic arrays,
Wu-Tung Cheng and Janak H. Patel,
International Journal of Computers and Mathematics with Applications, vol. 13, no. 5/6,
pp. 443-454, January 1987.

Testing in two-dimensional iterative logic arrays,
Wu-Tung Cheng and Janak H. Patel,
Proceedings of the International Symposium on Fault-Tolerant Computing,
pp. 76-81, July 1986.

Testing and error detection in iterative logic arrays,
Wu-Tung Cheng,
Ph.D. dissertation, Department of Computer Science,
Technical Report CSG-44/UILU-ENG-85-2234,
University of Illinois, 1985.

A shortest length test sequence for sequential-fault detection in ripple carry adders,
Wu-Tung Cheng and Janak H. Patel,
Proceedings of the International Conference on Computer-Aided Design,
pp. 71-73, November 1985.

Multiple-fault detection in iterative logic arrays,
Wu-Tung Cheng and Janak H. Patel,
Proceedings of the International Test Conference,
pp. 493-499, November 1985.

A minimum test set for multiple-fault detection in ripple carry adders,
Wu-Tung Cheng and Janak H. Patel,
Proceedings of the International Conference on Computer Design,
pp. 435-438, October 1985.