GATEST User Instructions

The GATEST sequential circuit test generation package includes three preprocessing programs, the test generator, and one shell script file, as described below:

To run the test generator, first place all executables in a "bin" directory, and include the pathname of that directory in your search path. Then create a TEST.run file with the "do_gatest" script file provided. Next, run the preprocessing programs, followed by the test generator. Program invocations for the s298 circuit are as follows:

do_gatest s298
level s298
faultlist
equiv
gatest -n 100 -v 32
Several options are available for GATEST which can be specified using the following command-line arguments: The number of vectors in a sequence (-v) should be specified by the user, since a good choice for this parameter depends on the circuit. A small multiple of the structural sequential depth would be a good place to start. The number of faults in the fault samples targeted (-n) should also be specified by the user since the full fault list is used by default, which may result in excessive execution times. The TEST.run file format is shown below:
simpic port number - port number for faultsim graphics
master host name - name of master host for graphics
bench file name - cir.bench (name of benchmark file -- level input)
cir file name - cir.lev (name of levelized circuit file -- level output)
vec file name - cir.vec (name of vector file -- faultsim input)
fault list - cir.fault (name of fault file -- faultlist output)
equiv fault list - cir.eqf (name of equivalent fault file -- equiv output)
undetected faults - cir.ufl (name of undetected fault file -- faultsim output)
faultsim host name - used with testgen (name of host for faultsim)
testgen host name - used with testgen (name of host for testgen)
name file - cir.name (name of "name" file -- level output)
atp file name - cir.atp (test vector file -- testgen output)
fsim res file - cir.frs faultsim results
tgen res file - cir.grs testgen results
sim gen port - port between faultsim and testgen
color - color graphics used if one
faultsim running - == 1 when running faultsim
testgen running - == 1 when testgen running
fault pic running - == 1 when graphics running
read vec - read cir.vec file before test generation if one
dominator - cir.dom (name of dominators file -- dominators output)
redundant - cir.red (name of file with untestable faults -- testgen output)
debug - debug value for testgen
backtrack limit - maximum number of backtracks allowed in testgen
state backtrack limit - maximum number of state backtracks allowed in testgen
time limit - maximum time allowed to generate a test in pass 1 (unit = 1/100 sec for HP, 1/60 sec for SUN)
scan stat - name of file for scan statistics
An example circuit description is shown below (ISCAS89 s27 circuit):
# 4 inputs
# 1 outputs
# 3 D-type flipflops
# 2 inverters
# 8 gates (1 ANDs + 1 NANDs + 2 ORs + 4 NORs)

INPUT(G0)
INPUT(G1)
INPUT(G2)
INPUT(G3)
OUTPUT(G17)
G5 = DFF(G10)
G6 = DFF(G11)
G7 = DFF(G13)
G14 = NOT(G0)
G17 = NOT(G11)
G8 = AND(G14, G6)
G15 = OR(G12, G8)
G16 = OR(G3, G8)
G9 = NAND(G16, G15)
G10 = NOR(G14, G11)
G11 = NOR(G5, G9)
G12 = NOR(G1, G7)
G13 = NOR(G2, G12)
A test vector file (.gat) for the example circuit is shown next.
4 <- number of primary inputs
1010 <- forced value for each primary input
1001
1000
0100
0001
0111
1001
0100
1111
1001
1001
1001
1001
0001
1001
1000
END <- end-of-file delimeter
The following component types are handled by GATEST:
INPUT
OUTPUT
DFF -- D flip flop
AND
NAND
OR
NOR
NOT -- inverter
BUF -- buffer, output = input
TIE1 -- line tied to 1
TIE0 -- line tied to 0
XOR -- exclusive-OR
XNOR -- exclusive-NOR
BUS -- bus, output goes to unknown if all inputs have Z value
BUS_GOHIGH -- bus, output goes to high if all inputs have Z value
BUS_GOLOW -- bus, output goes to low if all inputs have Z value
TRISTATE -- tristate, active low control signal
TRISTATEINV -- tristate with output inverted
TRISTATE1 -- tristate, active high control signal
MUX2 -- 2-input multiplexer

For the MUX2, TRISTATE, TRISTATEINV, and TRISTATE1 components, the control signal must be the last input in the list of inputs. In the multiplexer, the first input is selected when the control signal is 0, and the second input is selected when the control signal is 1. A bus component must have only tristate components as predecessors, and tristate components must have only bus components as successors. The bus output value is the value of the non-Z (high impedance) input. If there is a conflict (a one placed on one bus input and a zero placed on another bus input), the bus output value is unknown.


Last Updated: December 13, 1995
Send any questions to liz@uiuc.edu

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