GATEST: A Genetic-Algorithm-Based Test Generator for Sequential
Circuits
GATEST is a gate-level, simulation-based test generator
for sequential circuits which uses genetic algorithms (GAs) in evaluating
of candidate tests. Version 1.0 is currently being distributed to
non-profit educational institutions only. (Others please contact
Prof. Janak Patel for access.)
The program was designed to run under the Unix environment and has been
compiled for both HP and SUN workstations. It is available to the public
on an internal-use-only basis. The program targets single stuck-at faults
in synchronous sequential circuits described in the
ISCAS89 benchmark
format. Fault lists are automatically generated for all single stuck-at
faults in a circuit, and equivalence fault collapsing is performed using
structural equivalence. Several faults are targeted simultaneously by
GATEST. The GA generates candidate tests, and the PROOFS sequential
circuit fault simulator computes the fitness of each test; small fault
samples are used in the fitness computation to speed up the execution.
Tests evolve over several generations, and the best test is selected to
be added to the test set. PROOFS is then run, using the entire fault
list, to update the state of the circuit after the best test is
selected, and detected faults are removed from the fault list. GATEST
begins by generating individual test vectors and then proceeds to test
sequence generation when no more progress is made with the individual
test vectors. Several test sequence lengths are tried, in increasing
order, and the program terminates when no more improvements are made with
the test sequences.
Acknowledgement
The development of these tools was supported by the Semiconductor
Research Corporation.
Copyright © 1995 by the University of Illinois. All rights reserved.
Last Updated: September 10, 1997
Send any questions to liz@uiuc.edu