IGATE Design for Testability

Key Contributors

• Janak Patel
• Prith Banerjee
• Vivek Chickermane
• Frank Hsu
• Elizabeth Rudnick

Research Papers

A listing of all published IGATE research papers on design for testability is included below.

High-level variable selection for partial-scan implementation,
Frank F. Hsu and Janak H. Patel,
Proceedings of the International Conference on Computer-Aided Design, November 1998.

Partial scan selection based on dynamic reachability and observability information,
Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the International Conference on VLSI Design, January 1998.

Enhancing high-level control-flow for improved testability,
Frank Hsu, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the International Conference on Computer-Aided Design, pp. 322-328, November 1996.

Testability insertion in behavioral descriptions,
Frank Hsu, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the International Symposium on System Synthesis, pp. 139-144, November 1996.

A global algorithm for the partial scan design problem using circuit state information,
Dong Xiang and Janak H. Patel,
Proceedings of the International Test Conference, pp. 548-556, October 1996.

Partial scan design based on circuit state information,
Dong Xiang, Srikanth Venkataraman, W. Kent Fuchs, and Janak H. Patel,
Proceedings of the ACM/IEEE Design Automation Conference, pp. 807-812, June 1996.

Sequential circuit testability enhancement using a nonscan approach,
Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, and Janak H. Patel,
IEEE Transactions on VLSI Systems, vol. 3, no. 2, pp. 333-338, June 1995.
Abstract

A distance reduction approach to design for testability,
Frank Hsu and Janak H. Patel,
Proceedings of the IEEE VLSI Test Symposium, pp. 158-163, May 1995.

A genetic approach to test application time reduction for full scan and partial scan circuits,
Elizabeth M. Rudnick and Janak H. Patel,
Proceedings of the Eighth International Conference on VLSI Design, pp. 288-293, January 1995.

Simulation-based techniques for sequential circuit testing,
Elizabeth M. Rudnick,
Ph.D. dissertation, Department of Electrical and Computer Engineering, Technical Report CRHC-94-14/UILU-ENG-94-2229,
University of Illinois, August 1994.

An observability enhancement approach for improved testability and at-speed test,
Elizabeth M. Rudnick, Vivek Chickermane, and Janak H. Patel,
IEEE Transactions on Computer-Aided Design of Circuits and Systems, vol, 13, no. 8, pp. 1051-1056, August 1994.
Abstract

Addressing design for testability at the architectural level,
Vivek Chickermane, Jaushin Lee, and Janak H. Patel,
IEEE Transactions on Computer-Aided Design of Circuits and Systems, vol, 13, no. 7, pp. 920-934, July 1994.

A novel approach to improve testability of finite state machines,
Frank Fu-Chang Hsu,
M.S. thesis, Department of Electrical and Computer Engineering, University of Illinois, January 1994.

Non-scan design-for-testability techniques for sequential circuits,
Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, and Janak H. Patel,
Proceedings of the ACM/IEEE Design Automation Conference, pp. 236-241, June 1993.

Design and synthesis for testability using architectural descriptions,
Vivekanand Chickermane,
Ph.D. dissertation, Department of Electrical and Computer Engineering, Technical Report CRHC-93-10/UILU-ENG-93-2219,
University of Illinois, May 1993.

Impact of high level functional constraints on testability,
Jaushin Lee, Vivek Chickermane and Janak H. Patel,
Proceedings of the IEEE VLSI Test Symposium, pp. 309-312, April 1993.

A comparative study of design for testability methods using high-level and gate-level descriptions,
Vivek Chickermane, Jaushin Lee, and Janak H. Patel,
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 620-624, November 1992.

Design for testability using architectural descriptions,
Vivek Chickermane, Jaushin Lee, and Janak H. Patel,
Proceedings of the International Test Conference, pp. 752-761, September 1992.

APT: An area-performance-testability driven placement algorithm,
Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, and Janak H. Patel,
Proceedings of the Design Automation Conference, pp. 141-146, June 1992.

Probe point insertion for at-speed test,
Elizabeth M. Rudnick, Vivek Chickermane, and Janak H. Patel,
Proceedings of the VLSI Test Symposium, pp. 223-228, April 1992.

A fault-oriented partial scan design approach,
Vivek Chickermane and Janak H. Patel,
Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 400-403, November 1991.

An optimization based approach to the partial scan design problem,
Vivek Chickermane and Janak H. Patel,
Proceedings of the International Test Conference, pp. 377-386, September 1990.