IGATE Bridge Fault Testing

Key Contributors

• Janak Patel
• Elizabeth Rudnick
• James Cusey
• Gary Greenstein
• Frederick Gruner
• Jeffrey Rearick
• Jue Wu

Research Papers

A listing of all published IGATE research papers on bridge fault testng is included below.

Bridge fault diagnosis using stuck-at fault simulation,
Jue Wu and Elizabeth M. Rudnick, IEEE Transactions on Computer-Aided Design, vol. 19, no. 4, pp. 489-495, April 2000.

A fault list reduction approach for efficient bridge fault diagnosis,
Jue Wu, Gary S. Greenstein, and Elizabeth M. Rudnick, Proceedings of the Design, Automation and Test in Europe (DATE) Conference, pp. 780-781, March 1999.

A diagnostic fault simulator for fast diagnosis of bridge faults,
Jue Wu and Elizabeth M. Rudnick, Proceedings of the International Conference on VLSI Design, January 1999.

BART: A bridging fault test generator for sequential circuits
James P. Cusey and Janak H. Patel,
Proceedings of the International Test Conference, pp. 838-847, November 1997.

An efficient IDDQ test generation scheme for bridging faults in CMOS digital circuits,
Tzuhao Chen, Ibrahim N. Hajj, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the IEEE International Workshop on IDDQ Testing, pp. 74-78, October 1996.

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits,
Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the VLSI Test Symposium, pp. 456-462, April 1996.

L-Proofs: A leakage fault simulator for CMOS circuits
Frederick R. Gruner,
M.S. thesis, Department of Electrical and Computer Engineering, Technical Report CRHC-95-07/UILU-ENG-95-2205,
University of Illinois, February 1995.

Fast and accurate CMOS bridging fault simulation,
Jeffrey R. Rearick and Janak H. Patel,
Proceedings of the International Test Conference, pp. 54-61, October 1993.

A bridging-fault automatic resistance-based test generator,
James P. Cusey,
M.S. thesis, Department of Electrical and Computer Engineering, Technical Report CRHC-93-13/UILU-ENG-93-2223,
University of Illinois, June 1993.
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Fast and accurate CMOS bridging fault simulation,
Jeffrey R. Rearick,
M.S. thesis, Department of Electrical and Computer Engineering, Technical Report CRHC-93-03/UILU-ENG-93-2204,
University of Illinois, January 1993.

Accurate CMOS bridging fault simulation,
Janak H. Patel and Gary S. Greenstein,
Proceedings of the International Electron Devices and Materials Symposium, pp. 170-174, November 1992.

E-PROOFS: A CMOS bridging fault simulator,
Gary S. Greenstein and Janak H. Patel,
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 268-271, November 1992.
Abstract

CMOS bridging fault simulation,
Gary S. Greenstein,
M.S. thesis, Department of Electrical and Computer Engineering, Technical Report CRHC-92-07,
University of Illinois, April 1992.