|
|
|
Welcome to the ACS Simulation Tools install section.
Here, we provide the necessary steps to download, install,
and make use of our simulation tools.
|
|
|
| |
|
Running the Illinois Verilog Model
Download packages
First, download ivm-1.0.tar.gz.
Then, extract the files into a work directory on your
machine. While the software may run on other platforms, we have developed this software mainly on GNU/Linux/x86
platforms.
# cd {work_directory}
# tar -zxvf {path_to_downloads}/ivm-1.0.tar.gz
Compiling
IVM has been tested with two different compilers,
Synopsys VCS and
Icarus Verilog.
First, configure the makefile to use the desired compiler.
# cd IVM-1.0
# make target_icarus (for Icarus Verilog)
(or)
# make target_vcs (for Synopsys VCS)
After the makefile has been configured, just type "make".
# make
Running
There is no execution model/executable loader included with the small release,
so you will have to make your own instruction vectors in order to run any test programs.
The vectors should be in ASCII hexadecimal format, similar to the example file
here. Run the included vector translation script (perl required)
to convert the vectors into a format usable by the model. These files should be in the
same directory as the executable, and will be automatically loaded upon execution.
# ./make_icache_vectors.pl <vector_file>
# ./pipeline
|
Copyright 2004 Advanced Computing Systems (ACS). Feedback? Email
nwang@crhc.uiuc.edu.
|
|