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Welcome to the ACS Simulation Tools download section. Please take a look at our license for the terms and conditions of our software releases.

Illinois Verilog Model version 1.0

The Illinois Verilog Model (IVM) is a Verilog implementation of an Alpha microprocessor. The microarchitecture is a superscalar, dynamically scheduled pipeline, executing a subset of the Alpha instruction set. The processor includes such features as speculative instruction scheduling, memory dependence prediction, and sophosticated branch prediction. Up to 132 instructions can be in-flight in the 12-stage pipeline. Not including the caches and predictor tables, the processor core consists of approximately 50,000 bit elements of state (pipeline latches and RAM storage).

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Copyright 2004 Advanced Computing Systems (ACS). Feedback? Email nwang@crhc.uiuc.edu.