ACS Simulation Tools About IVM version 1.0

About IVM

The Illinois Verilog Model (IVM) is a Verilog implementation of an Alpha microprocessor at the Register Transfer Level. The microarchitecture is a superscalar, dynamically scheduled pipeline, executing a subset of the Alpha instruction set. We've verified the functional aspects of the design by comparison to an instruction-level reference model on real code streams (such as the SPEC benchmarks). The processor includes such features as speculative instruction scheduling, memory dependence prediction, and hybrid branch prediction. Up to 132 instructions can be in-flight in the 12-stage pipeline. Not including the caches and predictor tables, the processor core consists of approximately 50,000 bit elements of state (pipeline latches and RAM storage).

This RTL model is potentially useful to those doing microarchitectural studies. It also can serve as a large and complex benchmark design for automatic synthesis, test generation, and other advanced design tools.

The development of the Illinois Verilog Model was a fully supported activity of the Center for Circuits and Systems Solutions.

We have used IVM for developing transient-fault hardened microarchitectures, as described in the following publication:

• Nicholas J. Wang and Sanjay J. Patel,  
  "ReStore: Symptom Based Soft Error Detection in Microprocessors," [pdf]
  In the Proceedings of the 2005 International Conference on Dependable Systems and Networks, Yokohama, Japan, June 2005.

• Nicholas J. Wang, Justin Quek, Todd M. Rafacz, and Sanjay J. Patel,  
  "Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline," [pdf]
  In the Proceedings of the 2004 International Conference on Dependable Systems and Networks, Florence, Italy, June 2004.

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