Advanced Computing Systems (ACS)

Center for Reliable and High-Performance Computing

The University of Illinois at Urbana-Champaign

ACS is a research group focusing on future-generation computer architecture and systems.

Past Projects:

• rePLay : A Hardware Framework for Dynamic Optimization
• Techniques for Automatic Parallelization
• Soft-Error Rates
• Simulation Tools
• Architectural Support for High-Availability Systems

Professors:

• Sanjay Patel (sjp@crhc.uiuc.edu)

Graduate Students:

• Aqeel Mahesri (mahesri@crhc.uiuc.edu)

Ph.D. Alumni:

• Brian Fahs (bfahs@crhc.uiuc.edu), now at NVIDIA, Santa Clara, CA
• Nicholas Wang (nwang@crhc.uiuc.edu), now at NVIDIA, Santa Clara, CA

Masters Alumni:

• Satarupa Bose (satarupa@transmeta.com) formerly at Transmeta, Santa Clara, CA
• David Crowe (dcrowe@crhc.uiuc.edu) now at NVIDIA, Santa Clara, CA
• Matt Crum (mcrum@crhc.uiuc.edu) now at AMD, Austin, TX.
• Mike Fertig (fertig@crhc.uiuc.edu) now at AMD, Sunnyvale, CA
• Joseph Grzywacz (griz-whack) (grzywacz@crhc.uiuc.edu) now at NVIDIA, Santa Clara, CA
• Seth Herstad (herstad@crhc.uiuc.edu) now at AMD, Austin, TX
• Wojciech Magda (wmagda@crhc.uiuc.edu) now at Hewlett-Packard, Fort Collins, CO
• Ali Mushtaq (amushtaq@students.uiuc.edu)
• Greg Muthler (gmuthler@crhc.uiuc.edu) now at NVIDIA, Austin, TX.
• Jeffrey Namkung (jnamkung@crhc.uiuc.edu) now at NASA JPL, Pasadena, CA
• Justin Quek (quek@crhc.uiuc.edu) now at Intel, Portland, OR
• Todd Rafacz (trafacz@crhc.uiuc.edu) now at AMD, Austin, TX
• Galen Rasche (rasche@crhc.uiuc.edu) now at Southwest Research Institute, San Antonio, TX
• Kapil Sachdeva (ksachdev@crhc.uiuc.edu) now at Ohio State University College of Medicine
• Brian Slechta (slechta@crhc.uiuc.edu) now at Intel, Boston, MA
• Francesco Spadini (spadini@crhc.uiuc.edu) now at AMD, Austin, TX
• Tony Tung (tonytung@crhc.uiuc.edu) initially at Cisco Systems, Milpitas, CA
• Ashley Wise (awise@uiuc.edu)

Affiliated Faculty:

• Steve Lumetta (steve@crhc.uiuc.edu), UIUC
• Dan Friendly (friendly@cs.yale.edu), Yale University

Publications:

• Nicholas J. Wang, Aqeel Mahesri, and Sanjay J. Patel,  
  Examining ACE Analysis Reliability Estimates Using Fault Injection, [pdf]
  In the Proceedings of the 34th Annual International Symposium on Computer Architecture, San Diego, California, June 2007.

• Wen-mei Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel A. Mahesri, Stephanie C. Tsao, Nacho Navarro, Steve S. Lumetta, Matthew I. Frank, and Sanjay J. Patel,  
  Implicit Parallel Programming Models for Thousand-Core Microprocessors, [pdf]
  In the Proceedings of the 44th Annual Design Automation Conference, San Diego, California, June 2007.

• Aqeel Mahesri, Nicholas J. Wang, and Sanjay J. Patel,  
  Hardware Support for Software Controlled Multithreading, [pdf]
  In the Workshop on Design, Architecture, and Simulation of Chip Multi-Processors, December 2006.

• Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, and Sanjay J. Patel,  
  Sequential Element Design With Built-In Soft Error Resilience, [pdf]
  In IEEE Transactions on Very Large Scale Integration Systems, December 2006.

• Nicholas J. Wang and Sanjay J. Patel,  
  ReStore: Symptom-Based Soft Error Detection in Microprocessors, [pdf]
  In IEEE Transactions on Dependable and Secure Computing, July-September 2006.

• Giacinto P. Saggese, Nicholas J. Wang, Zbigniew T. Kalbarczyk, Sanjay J. Patel, and Ravishankar K. Iyer,  
  An Experimental Study of Soft Errors in Microprocessors, [pdf]
  In IEEE Micro, November 2005.

• Aqeel Mahesri and Sanjay J. Patel,  
  Exploiting Parallelism Between Control and Data Computation, [pdf][ps]
  University of Illinois Technical Report, UILU-ENG-05-2214, September 2005.

• Brian Fahs, Todd Rafacz, Sanjay J. Patel, and Steven S. Lumetta,  
  Continuous Optimization, [pdf]
  In the Proceedings of the 32nd Annual International Symposium on Computer Architecture, Madison, Wisconsin, June 2005.

• Nicholas J. Wang and Sanjay J. Patel,  
  ReStore: Symptom Based Soft Error Detection in Microprocessors, [pdf]
  In the Proceedings of the 2005 International Conference on Dependable Systems and Networks, Yokohama, Japan, June 2005.

• Brian Fahs, Aqeel Mahesri, Francesco Spadini, Sanjay J. Patel, and Steven S. Lumetta,  
  The Performance Potential of Trace-based Dynamic Optimization, [pdf][ps]
  University of Illinois Technical Report, UILU-ENG-04-2208, November 2004.

• Brian Fahs, Todd Rafacz, Sanjay J. Patel, and Steven S. Lumetta,  
  Continuous Optimization, [pdf][ps]
  University of Illinois Technical Report, UILU-ENG-04-2207, August 2004.

• Nicholas J. Wang, Justin Quek, Todd M. Rafacz, and Sanjay J. Patel,  
  Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline, [pdf]
  In the Proceedings of the 2004 International Conference on Dependable Systems and Networks, Florence, Italy, June 2004.

• Todd Ehrhart and Sanjay J. Patel,  
  Reducing the Scheduling Critical Cycle using Wakeup Prediction, [pdf]
  In the Proceedings of the 10th International Symposium on High-Performance Computer Architecture, Madrid, Spain, February 2004.

• Nicholas Wang, Michael Fertig, and Sanjay J. Patel,  
  Y-Branches: When You Come to a Fork in the Road, Take It, [pdf]
  In the  Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, New Orleans, LA, Sept 2003

• F. Spadini, B. Fahs, S. J. Patel, and S. S. Lumetta,
  Improving Quasi-Dynamic Schedules Through Region Slip [pdf]
  In the Proceedings of the First International Symposium on Code Generation and Optimization, April 2003.  

• B. Slechta, D. Crowe, B. Fahs, M. Fertig, G. A. Muthler, J. Quek, F. Spadini, S. J. Patel, and S. S. Lumetta,
  Dynamic Optimization of Micro-Operations [pdf]
  In the Proceedings of the 9th International Symposium on High-Performance Computer Architecture, February 2003.  

• F. Spadini, M. Fertig, and S. J. Patel,
  Characterization of Repeating Dynamic Code Fragments, [pdf]
  University of Illinois Technical Report, CRHC-02-09, December 2002.

• G. A. Muthler, D. Crowe, S. J. Patel, and S. S. Lumetta,
  Instruction Fetch Deferral using Static Slack, [pdf]
  In the Proceedings of the 35th ACM/IEEE International Symposium on Microarchitecture, November 2002.  

• B. Fahs, S. Bose, M. M. Crum, B. Slechta, F. Spadini, T. Tung, S. J. Patel, and S. S. Lumetta
  Performance Characterization of a Hardware Mechanism for Dynamic Optimization [pdf]
  In the Proceedings of the 34rd ACM/IEEE International Symposium on Microarchitecture, December 2001.  

• S. J. Patel, T. Tung, S. Bose, and M. M. Crum
  Increasing the Size of Atomic Instruction Blocks using Control Flow Assertions [pdf] [ps]
  In the Proceedings of the 33rd ACM/IEEE International Symposium on Microarchitecture, December 2000.

• S. J. Patel and S. S. Lumetta
  rePLay : a Hardware Framework for Dynamic Program Optimization [pdf] [ps]
  University of Illinois Technical Report, CRHC-99-16, December 1999.

Doctoral Dissertations:

• Brian Fahs
  Dynamic Optimization in Hardware [pdf]
  Ph.D. Dissertation, December 2005.  

• Nicholas J. Wang
  Cost Effective Soft Error Mitigation in Microprocessors [pdf]
  Ph.D. Dissertation, August 2007.  

Masters Theses:

• Satarupa Bose
  Exploiting Value Invariance with Frame Specialization [ps]
  M.S. thesis, May 2001.  

• Matthew Martin Crum
  Design Alternatives for Caching Long Regions of the Dynamic Instruction Stream [pdf] [ps]
  M.S. thesis, May 2001.  

• David Crowe
  Flipper: Branch Reversal Using Misprediction Distance [pdf]
  M.S. thesis, May 2004.  

• Brian Fahs
  An Analysis of a Novel Approach to Dynamic Optimization [pdf] [ps]
  M.S. thesis, May 2003.

• Mike Fertig
  Performance Implications of Future-Generation Memory Systems Technology [pdf] [ps]
  M.S. thesis, August 2003.  

• Joseph E. Grzywacz
  Dynamically Dead Regions [pdf] [ps]
  M.S. thesis, May 2005.  

• Seth Herstad
  Evaluation of a Data Prefetching Method for a Second-Level Cache [pdf] [ps]
  M.S. thesis, December 2003.  

• Wojciech Magda
  Evaluating the Impact of Noise On Microprocessor Operation Using an RTL Model [pdf]
  M.S. thesis, 2002.  

• Aqeel Mahesri
  Exploiting Control/Data Parallelism [pdf] [ps]
  M.S. thesis, May 2004.  

• Gregory A. Muthler
  Fetch Tokens: A method for improving single-thread performance on a chip-multiprocessor [pdf]
  M.S. thesis, December 2004.

• Jeffrey Namkung
  An Event-level Power Measurement and Analysis Methodology [pdf]
  M.S. thesis, May 2001.  

• Todd Rafacz
  Spawn Point Prediction for a Polyflow Processor [pdf]
  M.S. thesis, May 2005.  

• Galen Rasche
  The Header-Trailer Trace Cache: Efficiently Storing Multipath Traces [pdf]
  M.S. thesis, December 2004.  

• Kapil Sachdeva
  Load Values and the Branches That Use Them [pdf] [ps]
  M.S. thesis, May 2005.  

• Brian Slechta
  The rePLay Transmogrifier: a Framework for the Decode and Execution of ISA Instructions [pdf] [ps]
  M.S. thesis, December 2003.  

• Francesco Spadini
  Idiom Analysis: A Novel Approach to Dataflow Redundancy Identification [pdf]
  M.S. thesis, May 2006.  

• Yen-Ting Tony Tung
  Fetch Reordering and Partitioning of Execution Resources for Atomic Instruction Blocks with Control Flow Assertions [pdf] [ps]
  M.S. thesis, May 2001.

• Nicholas Wang
  Characterizing Logical Masking of Transient Faults at the Microarchitectural and Architectural Levels [pdf]
  M.S. thesis, December 2003.  

• Ashley Wise
  Configurable Dynamic Hardware Prefetching of Linked Data Structures with a Pointer Cache [pdf]
  M.S. thesis, May 2003.  

Corporate Sponsors:

• AMD
• Intel
• IBM
• HP
• Sun Microsystems, Inc.

Last updated 03-Feb-2003 14:40