---

Sanjay J. Patel
Associate Professor of Electrical and Computer Engineering
262 Coordinated Sciences Laboratory, MC 228
1308 West Main St.
Urbana, IL 61801-2307
Phone 217.333.9219
FAX 217.244.5685
sjp at uiuc edu

On-leave during 2005-2006 Academic Year at AGEIA Technologies

Curriculum Vitae

Research Interests

My research group -- the Advanced Computing Systems Group -- develops enabling technology 
for future generation computing systems.  We are developing computer architectures that deliver high 
performance at low power and operate in a highly reliable manner.  

We have several on-going projects at various stages of maturity. Several of the projects below have
significant industrial funding, and are in cooperation with processor research and design groups at
Intel, AMD, IBM, and Sun. We also have funding from the C2S2 MARCO center, which is a
semiconductor research consortium between industry, academia, and DARPA. Our objective is to
investigate and develop commercially-relevant technologies for use in future generation processors.

rePLay Framework : Frame-based Hardware-based Dynamic Optimization.

Robust Microarchitecture: Developing the tools and know-how to build cost-effective transient-error tolerant microarchitectures.

Control/Data Decoupling: A new architectural model for exploiting parallelism between control and data operations in a single thread of execution.

Polyflow: A processor model for 2014, targeting 10-way parallelism on control-intensive code.

During the course of our work on these projects, we’ve developed a set of tools that we are making
available for others to use. Check out the ACS Tools Page for more details.

Selected Publications

Dynamic Optimization
Trace Caches
Branch Prediction
Processor Technology
Reliable Systems Design

Teaching Interests

Intro Computing: Introduction to Computing Systems: From Bits and Gates to C and Beyond

ECE 190: Introduction to Computing Systems

ECE 425: Introduction to VLSI System Design

ECE 411: Computer Organization and Design

ECE 511: Computer Architecture

ECE 512: High-Performance Microarchitecture: Hardware and Software

Professional Biography

Sanjay J. Patel is an Associate Professor of Electrical and Computer Engineering and Willett Faculty Scholar at the University of Illinois at Urbana-Champaign. He is the co-author (with Yale N. Patt of The University of Texas at Austin) of an introductory textbook for computer science and engineering students, titled "Introduction to Computing Systems: From Bits and Gates to C and Beyond", which is now available in its second edition from McGraw-Hill.

His research interests include processor microarchitecture, computer architecture, and high performance and reliable computer systems. In particular, his research group, the Advanced Computing Systems Group, investigates high-performance and error-tolerant processor architectures for the 7 to 10 year time horizon. He and his group are developing key instruction optimization technology that will be used in next-generation high-performance microprocessors. Patel has published over 30 articles and papers in the area.

He has done architecture, hardware verification, logic design, and performance modeling at Digital Equipment Corporation, Intel Corporation, and HAL Computer Systems, as well as provided consultation for Transmeta, Jet Propulsion Laboratory, HAL, Intel, and AGEIA Technologies. He is currently serving as Chief Architect at AGEIA Technologies.

Patel earned his Bachelor (1990), Master of Science (1992) and Ph.D. (1999) in Computer Science and Engineering from the University of Michigan, Ann Arbor.