ECE 462 (Spring 2005) - Homework 4
Assigned Feb. 18
Due in class on Feb. 25

Grading policy

	Answers to only a subset of the questions will be graded for
	correctness of the answer and the procedure. Credit will be
        granted for attempting the other questions.

Readings: Sections 5.5, 5.6, 3.6


1. Problem 5.14 (show that the right hand sides of the two definitions
	in the problem are equal)

2.  Problem 5.15(b) and 5.15(c)

3.  Problem 5.16(a) and 5.16(b)

4.  Problem 5.18(a)

5.  Problem 3.8

6.  For the circuit in Figure P3.11(a) (i.e., the circuit in Problem 3.11
	on page 97)
	(i) Determine the 1-sets and 0-sets
	(ii) Plot the 1-sets and 0-sets on Karnaugh maps
	(iii) Determine all static logic hazards, if any, using the 1-sets
		or the 0-sets.

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Suggested exercise (you do not need to turn in the solution to the
question below in your homework 4):

For the hazards found in question 5 above, show a timing diagram to
illustrate how the hazard may occur.